The present invention relates to semiconductor devices, and more specifically to a method of fabricating a power semiconductor device and a semiconductor high voltage switch in which a sacrificial N shelf layer is grown on a P+semiconductor substrate to alleviate a change in integrated dopant level of an N+buffer layer atop the shelf layer due to out-diffusion of dopant from the substrate.
Semiconductor devices, such as high voltage switches (e.g., 600 to 1200 volt Insulated Gate Bipolar Transistors), are manufactured to meet predetermined specifications which are desirably narrowly defined (that is, there is little tolerance for variation in the finished devices.) However, device fabrication processing introduces variations which may cause some devices to fail to meet specifications, reducing device yield. By way of example, one such specification is the 1200V IGBT conductivity measurement, collector emitter saturation voltage V.sub.CE(SAT) (sometimes denoted V.sub.CE(ON)), which is desirably kept low--on the order of 2.0 to 3.0 volts--and tightly distributed about a desired voltage.
In some devices, such as high voltage switches, V.sub.CE(SAT) may vary unacceptably so as to cause low device yields, although it has been found that the severity of the V.sub.CE(SAT) variations may be controlled, at least in part, during the device manufacturing process. For example and with reference to FIG. 1, the manufacture of high voltage switches may include growing an N+ buffer layer 12 between a P+ substrate 14 and an N- epitaxial layer 16 (the structure shown is a portion of a switch, the remainder of the switch structure being unrelated to the present invention and known in the art.) It has been found that the V.sub.CE(SAT) variations get worse as the starting dopant level and thickness of the buffer layer 12 increase, especially after lifetime control is performed (integrated dopant level is a term also used in this regard, where integrated dopant level is the integral of the layer dopant level over layer thickness.) Irradiation or any other method of lifetime control of a semiconductor device during fabrication affects the variability of some of its characteristics. Irradiation is used to control carrier lifetime, typically occurs late in the device fabrication process, and inevitably causes some variability in device characteristics. The variability is amplified if the dopant level and thickness of buffer layer 12 also vary so as to cause the integrated dopant level to vary. Therefore it is desirable to control the buffer layer 12 integrated dopant level so that all devices have characteristics which are tightly distributed about desired levels.
As will be appreciated, the desired integrated dopant level of buffer layer 12 in the finished semiconductor device drives the selection of the starting dopant level, thickness and irradiation dose, and there are trade-offs which can be made to achieve the desired result. For example, the irradiation dose may be kept low and the starting dopant level and/or thickness increased commensurately. The starting dopant level and/or thickness is increased because during device fabrication (e.g., epitaxial growth, high temperature drives) dopant from substrate 14 out-diffuses into buffer layer 12 reducing its thickness and/or dopant level (that is, some of the N type region is overwhelmed by P type dopant.) In the prior art the starting dopant level and layer thickness thus are initially larger than needed to account for this shrinkage. It would be desirable to avoid the higher starting dopant level and increased buffer layer thickness (and attendant high integrated dopant level) while maintaining a low irradiation dose to make the process of epitaxial growth more manufacturable.
If the effect of the out-diffusion on the N+ buffer layer can be reduced (the out-diffusion itself cannot be stopped), the starting dopant level and buffer layer thickness (and irradiation dose) may be kept low. When these are kept low the V.sub.CE(SAT) variations may be controlled so that the specification for V.sub.CE(SAT) and other characteristics may be met more easily in the finished product.
By way of further background, semiconductor switches desirably have a fast turn-off capability, in some power devices several hundred nanoseconds. One of the factors determining turn-off speed is the doping level adjacent the PN junction 18 between substrate 14 and buffer layer 12. High doping levels in this area allow the switch to operate with acceptably fast turnoff speeds, while low doping levels adjacent PN junction 18 do not.
The prior art has not been able to mass produce such epitaxial-based and lifetime controlled semiconductor power switches which have V.sub.CE(SAT) S which are tightly distributed about a desired voltage, and which have fast turn-off speeds. The tight control of the integrated dopant level of N+ buffer layer 12 has been incompatible with the need to provide high dopant levels adjacent PN junction 18.
Accordingly, it is an object of the present invention to provide a novel method of manufacturing a semiconductor device which obviates the problems of the prior art.
It is another object of the present invention to provide a novel method of manufacturing a semiconductor device in which a sacrificial shelf layer is grown on a substrate to alleviate a reduction in integrated dopant level in a buffer layer atop the shelf layer due to out-diffusion of dopant from the substrate.
It is yet another object of the present invention to provide a novel method of reducing variability of V.sub.CE(SAT) in a semiconductor device caused during manufacture of the device by growing a shelf layer between a substrate and an overlying buffer layer, the shelf layer being provided with a dopant level less than a dopant level of the overlying buffer layer so that the shelf layer absorbs out-diffusion of dopant from the substrate during subsequent device processing with little change in the net N+ buffer integrated dopant level.
It is still another object of the present invention to provide a novel method of alleviating a reduction in the integrated dopant level of an N+ buffer layer by growing an N shelf layer between the N+ buffer layer and the substrate, and doping the shelf layer to a level one to two orders of magnitude less than the dopant level of the buffer layer and of the dopant level of the substrate.
It is a further object of the present invention to provide a novel method of manufacturing a semiconductor device in which a desired integrated dopant level is provided in a thinner N+ buffer layer than available in the prior art while preventing P+ substrate diffusion through the N+buffer layer.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.